1 ps8448 10/10/00 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 vccn fb vccn 2q1 2q0 3f0 fs vccq ref gnd test 2f1 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 3 2 1 32 31 30 product features four pairs of programmable skew outputs 3.75 to 80 mhz output operation user-selectable output functions: - selectable skews - inverted and noninverted - operation at ? and ? input frequency - operation at 2x and 4x input frequency low skew <100ps typical, same pair. 250ps max. allow ref clock input to have spread spectrum modulation for emi reduction 2x, 4x, ? and ? outputs 3-level inputs for skew and output frequency control external feedback, internal loop filter low cycle-to-cycle jitter: <25ps rms duty cycle of output clock signals: 45% min. 55% max. compatible with pentium based processor same pinout as cypress cy7b991 packaged in plastic 32-pin plcc package description the pi6c991 is a low-skew, low jitter, 5v phase-lock loop (pll) programmable skew clock driver, for high performance comput- ing and networking applications. this part offers user selectable skew-control of 4 output pairs, providing the timing delays neces- sary to optimize high performance clock distribution circuits. each output can be hardwired to one of nine delay or function configurations. delay increments are determined by the input clock frequency and the configurations selected by the user. the pi6c991 allows the ref clock input to have spread spectrum modulation for emi reduction. the pi6c991 is pin-compatible with cypress roboclock cy7b991, with improved ac/dc characteristics. logic block diagram pin configuration 32-pin j 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c991 5v high-speed programmable skew clock buffer - superclock tm vco and time unit generator filter phase freq det test fs fb ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 three level select inputs skew select matrix 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1
2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm e m a n l a n g i so / in o i t p i r c s e d f e r i g n i m i t d n a y c n e u q e r f e h t s e i l p p u s t u p n i s i h t . t u p n i y c n e u q e r f e c n e r e f e r . d e r u s a e m s i n o i t a i r a v l a n o i t c n u f l l a h c i h w e c n e r e f e r b f . ) s t u p t u o t h g i e e h t f o e n o o t d e t c e n n o c y l l a c i p y t ( t u p n i k c a b d e e f l l p s f. t c e l e s e g n a r y c n e u q e r f l e v e l - e e r h t 1 e l b a t e e s . 1 f 1 , 0 f 1 . ) 1 q 1 , 0 q 1 ( 1 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 2 e l b a t e e s . 1 f 2 , 0 f 2 . ) 1 q 2 , 0 q 2 ( 2 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 2 e l b a t e e s . 1 f 3 , 0 f 3 . ) 1 q 3 , 0 q 3 ( 3 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 2 e l b a t e e s . 1 f 4 , 0 f 4 . ) 1 q 4 , 0 q 4 ( 4 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 2 e l b a t e e s . t s e t . s n o i t p i r c s e d m a r g a i d k c o l b e h t r e d n u n o i t c e s e d o m t s e t e e s . t c e l e s l e v e l - e e r h t 1 q 1 , 0 q 1 o . 1 r i a p t u p t u o 2 e l b a t e e s . 1 q 2 , 0 q 2. 2 r i a p t u p t u o 2 e l b a t e e s . 1 q 3 , 0 q 3. 3 r i a p t u p t u o 2 e l b a t e e s . 1 q 4 , 0 q 4. 4 r i a p t u p t u o 2 e l b a t e e s . v n c c r w p . s r e v i r d t u p t u o r o f y l p p u s r e w o p v q c c . y r t i u c r i c l a n r e t n i r o f y l p p u s r e w o p d n gd n u o r g pin definitions block diagram description phase frequency detector and filter these two blocks accept input signals from the reference frequency (ref) input and the feedback (fb) input and generate correction information to control the frequency of the voltage-controlled oscillator (vco). these blocks, along with the vco, form a phase- locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew mix matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the level of the fs pin as shown in table 1. skew select matrix the skew select matrix is comprised of four independent sections. each section has two low-skew, high-fanout drivers (xq0, xq1), and two corresponding three-level function select (xf0, xf1) inputs. table 2 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected.
3 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm s f ) 3 , 2 ( f m o n ) z h m ( e t a m i x o r p p a y c n e u q e r f t a ) z h m ( h c i h w t u s n 0 . 1 = . n i m. x a m w o l5 10 34 47 . 2 2 d i m5 20 56 25 . 8 3 h g i h0 40 0 16 15 . 2 6 table 1. frequency range select and t u calculation (1) table 2. programmable skew configurations (1) s t c e l e s n o i t c n u fs n o i t c n u f t u p t u o , 1 f 2 , 1 f 1 1 f 4 , 1 f 3 , 0 f 2 , 0 f 1 0 f 4 , 0 f 3 , 1 q 1 , 0 q 1 1 q 2 , 0 q 2 1 q 3 , 0 q 3 , 0 q 4 1 q 4 w o l w o lt 4 - u 2 y b e d i v i d d i mt 3 - u t 6 - u h g i ht 2 - u t 4 - u d i m w o lt 1 - u t 2 - u d i mt 0 - u h g i ht 1 + u t 2 + u h g i h w o lt 2 + u t 4 + u d i mt 3 + u t 6 + u h g i ht 4 + u 4 y b e d i v i dd e t r e v n i figure 1. typical outputs with fb connected to a zero-skew output (4) (n/a) lm -6t u ll lh -4t u lm (n/a) -3t u lh ml -2t u ml (n/a) -1t u mm mm 0t u mh (n/a) +1t u hl mh +2t u hm (n/a) +3t u hh hl +4t u (n/a) hm +6t u t 0 -6t u t 0 -5t u t 0 -4t u t 0 -3t u t 0 -2t u t 0 -1t u t 0 t 0 +1t u t 0 +2t u t 0 +3t u t 0 +4t u t 0 +5t u t 0 +6t u (n/a) ll/hh divided (n/a) hh invert fb input ref input 1fx 2fx 3fx 4fx 1 f nom x n where n= t u =
4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm test mode the test input is a three-level input. in normal system operation, this pin is connected to ground, allowing the pi6c991 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied low through a 100 w resistor. this will allow an external tester to change the state of these pins). if the test input is forced to its mid or high state, the device will operate with its internal phase locked loop disconnected, and in- put levels supplied to ref will directly control all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operation (test tied low). all outputs will function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. maximum ratings (above which the useful life may be impaired) storage temperature ............................................ C65oc to +150oc ambient temperature with power applied .............................................. C55oc to +125oc supply voltage to ground potential ....................... C0.5v to +7.0v dc input voltage .................................................... C0.5v to +7.0v output current into outputs (low) ................................... 64ma static discharge voltage (per mil-std-883, method 3015) ................................. >2001v latch-up current ............................................................ >200ma e g n a r t n e i b m a e r u t a r e p m e t v c c l a i c r e m m o cc o 0 7 + o t c o 0% 0 1 v 5 l a i r t s u d n ic o 5 8 + o t c o 0 4 C% 0 1 v 5 operating range notes for tables on pages 3 through 7: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connections to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the normal operating frequency (f nom ) of the v co and the time unit generator (see logic block diagram). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see table 2). the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power-up until v cc has reached 2.8v. 4. fb connected to an output selected for zero skew (ie., xf1 = xf0 = mid). 6. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors holds unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all datasheet limits are achieved. 7. the part should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room tempe rature only. 11. test measurement levels are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2ns or less and out put loading as shown in the ac test loads and waveforms unless otherwise specified. 12. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 13. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 30pf and terminated with 50 w to 2.06v. 14. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 15. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 16. c l = 0pf. for c l = 30pf, t skew0 = 0.35ns 17. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 18. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.). 19. t odcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. 20. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 21. t orise and t ofall measured between 0.8v and 2.0v. 22. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
5 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. x a ms t i n u v h o e g a t l o v h g i h t u p t u ov c c i , n i m = h o a m 6 1 C =4 . 2 v v l o e g a t l o v w o l t u p t u ov c c i , n i m = l o a m 6 4 =5 4 . 0 v h i s t u p n i b f , f e r f o e g a t l o v h g i h t u p n i 0 . 2v c c v l i s t u p n i b f , f e r f o e g a t l o v w o l t u p n i 5 . 0 C8 . 0 v 3 h i f o e g a t l o v h g i h t u p n i n f x , s f , t s e t s t u p n i l e v e l - 3 ) 6 ( n i m v c c x a m v c c 5 8 . 0 Cv c c v 3 m i f o e g a t l o v d i m t u p n i n f x , s f , t s e t s t u p n i l e v e l - 3 ) 6 ( v c c 5 . 0 C 2 /v c c 5 . 0 + 2 / v 3 l i f o e g a t l o v w o l t u p n i n f x , s f , t s e t s t u p n i l e v e l - 3 ) 6 ( 5 8 . 0 i | n i | t n e r r u c e g a k a e l t u p n i s t u p n i b f , f e r f o v n i v = c c v 4 . 0 r o v c c x a m = 0 1 m a i | 3 | t n e r r u c c d t u p n i l e v e l - 3 ) 0 : 1 f n , s f , t s e t ( v n i v = c c ) l e v e l h g i h (0 0 2 v n i v = c c ) l e v e l d i m ( 2 /0 5 v n i ) l e v e l w o l ( d n g =0 0 2 i s o t n e r r u c t i u c r i c t r o h s ) 7 ( v c c v , x a m = t u o d n g = ) y l n o o 5 2 ( 0 5 2 C a m i q c c y b d e s u t n e r r u c g n i t a r e p o y r t i u c r i c l a n r e t n i v n c c v = q c c , x a m = n e p o s t c e l e s t u p n i l l a 5 8 i n c c r i a p t u p t u o r e p t n e r r u c r e f f u b t u p t u o v n c c v = q c c , x a m = i t u o a m 0 = f , n e p o s t c e l e s t u p n i x a m 4 1 d pr i a p t u p t u o r e p n o i t a p i s s i d r e w o p 8 7 dc characteristics over the operating range
6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. x a ms t i n u c n i t u p n i e c n a t i c a p a c t a , z h m 1 = f , c o 5 2 = v c c v 0 . 5 = 0 1f p capacitance at ref and fb ac test loads and waveforms (pi6c991) 5v r1 r2 r1 = 130 w r2=91 w c l = 30pf (includes fixture and probe capacitance) c l ttl ac test load (16) ttl input test waveform 1ns 1ns 2.0v v th = 1.5v 0.8v 2.0v v th = 1.5v 0.8v 0.0v 3.0v
7 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm r e t e m a r a pn o i t p i r c s e d 2 - 1 9 9 c 6 i p5 - 1 9 9 c 6 i p1 9 9 c 6 i p . n i m. p y t. x a m. n i m. p y t. x a m. n i m. p y t. x a m f m o n k c o l c g n i t a r e p o z h m n i y c n e u q e r f w o l = s f ) 2 , 1 ( 5 10 35 10 35 10 3 d i m = s f ) 2 , 1 ( 5 20 55 20 55 20 5 h g i h = s f ) 3 , 2 , 1 ( 0 40 80 40 80 40 8 t h w p r h g i h h t d i w e s l u p f e r 0 . 50 . 50 . 5 t l w p r w o l h t d i w e s l u p f e r t u t i n u w e k s e l b a m m a r g o r p 1 e l b a t e e s t r p w e k s ) 1 q x , 0 q x ( w e k s r i a p - d e h c t a m t u p t u o o r e z ) 4 1 , 3 1 ( 5 0 . 00 2 . 01 . 05 2 . 01 . 05 2 . 0 t 0 w e k s ) s t u p t u o l l a ( w e k s t u p t u o o r e z ) 5 1 , 3 1 ( 0 1 . 05 2 . 05 2 . 05 . 03 . 05 7 . 0 t 1 w e k s ) s t u p t u o s s a l c e m a s , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 7 1 , 3 1 ( 5 2 . 05 . 06 . 07 . 06 . 00 . 1 t 2 w e k s ) d e d i v i d - d e d i v i d , d e t r e v n i - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 7 1 , 3 1 ( 0 3 . 05 . 00 5 . 00 . 10 . 15 . 1 t 3 w e k s ) s t u p t u o s s a l c t n e r e f f i d , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 7 1 , 3 1 ( 5 2 . 05 . 00 5 . 07 . 07 . 02 . 1 t 4 w e k s ) d e t r e v n i - d e d i v i d , d e d i v i d - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 7 1 , 3 1 ( 0 5 . 09 . 00 5 . 00 . 12 . 17 . 1 t v e d w e k s e c i v e d - o t - e c i v e d ) 8 1 , 2 1 ( 5 7 . 05 2 . 15 6 . 1 t d p e s i r b f o t e s i r f e r , y a l e d n o i t a g a p o r p5 2 . 0 C05 2 . 05 . 0 C05 . 07 . 0 C0 . 07 . 0 + t v c d o n o i t a i r a v e l c y c y t u d t u p t u o ) 9 1 ( 5 6 . 0 C05 6 . 00 . 1 C00 . 12 . 1 C0 . 02 . 1 + t h w p % 0 5 m o r f n o i t a i v e d e m i t h g i h t u p t u o ) 0 2 ( 0 . 20 . 20 . 3 t l w p % 0 5 m o r f n o i t a i v e d e m i t w o l t u p t u o ) 0 2 ( 5 . 15 . 25 . 3 t e s i r o e m i t e s i r t u p t u o ) 1 2 ( 5 1 . 00 . 12 . 15 1 . 00 . 15 . 15 1 . 05 . 15 . 2 t l l a f o e m i t l l a f t u p t u o ) 1 2 ( 5 1 . 00 . 12 . 15 1 . 00 . 15 . 15 1 . 05 . 15 . 2 t k c o l e m i t k c o l l l p ) 2 2 ( 5 . 05 . 05 . 0 t r j t u p t u o e l c y c o t - e l c y c r e t t i j s m r ) 2 1 ( 5 25 25 2 k a e p - o t - k a e p ) 2 1 ( 0 0 20 0 20 0 2 switching characteristics over the operating range (2,11)
8 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm ac timing diagrams ref fb q other q inverted q ref divided by 2 ref divided by 4 t ref t rpwl t rpwh t pd t odcv t skewpr, t skew0,1 t skewpr, t skew0,1 t skew2 t skew3,4 t skew3,4 t skew3,4 t skew3,4 t skew2,4 t skew2 t odcv t jr
9 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8448 10/10/00 pi6c991 5v high speed programmable skew clock buffer - superclock tm pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com package diagram 32-pin plcc (j32) x.xx x.xx denotes dimensions in millimeters .100 .140 .013 .021 .065 .095 1.524 2.413 .026 .032 0.661 0.812 .490 .530 .390 .430 .015 0.381 min. .025 .045 typ. pin 1 .485 .495 .547 .553 13.894 14.046 .045 .447 .453 11.354 11.506 1.143 .050 1.27 .585 .595 14.859 15.113 typ. bsc 12.319 12.573 2.450 3.556 0.331 0.533 9.906 10.922 12.446 13.462 1.143 0.635 typ. ordering information ) s p ( y c a r u c c ae d o c g n i r e d r o e g a k c a p e m a n e g a k c a p e p y t g n i t a r e p o e g n a r 0 5 2j 2 - 1 9 9 c 6 i p 2 3 j d e d a e l c i t s a l p d a e l - 2 3 ) c c l p ( r e i r r a c p i h c l a i c r e m m o c 0 0 5j 5 - 1 9 9 c 6 i p j i 5 - 1 9 9 c 6 i pl a i r t s u d n i 0 5 7j 1 9 9 c 6 i pl a i c r e m m o c j i - 1 9 9 c 6 i pl a i r t s u d n i
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